(153)
MSKS 0 D00100
0000
00
386
Example In the following example, inputs 0 to 3 of Interrupt Input Unit 0 are unmasked,
and inputs 4 to 7 are masked when CIO 000000 is ON.
Address Instruction Operands
00000 LD 000000
00001 MSKS(153)
0
D00100
D00100
D00101
0 0 F 0
0 0 F 2
5-31-2 CLEAR INTERRUPT: CLI(154)
(154)
CLI N S
S: Data source word CIO, G, A, T, C, #, DM, DR, IR
N: Interrupt source # (0 to 5)
Operand Data AreasLadder Symbol
Variations
j CLI(154)
When the execution condition is OFF, CLI(154) is not executed. When the ex-
ecution condition is ON, CLI(154) clears the recorded interrupts of the desig-
nated Interrupt Input Unit if N is 0 to 3, or sets the time to the first scheduled inter-
rupt if N is 4 or 5.
N specifies the interrupt. Numbers 0 to 3 indicate I/O Interrupt Input Units 0 to 3,
and numbers 4 and 5 indicate scheduled interrupts 0 and 1, respectively. The
CV500 or CVM1-CPU01-EV2 has scheduled interrupt 0 only.
Because interrupt inputs are stored, masked interrupts will be serviced after the
mask is removed, unless they are cleared first. If N designates an Interrupt Input
Unit, CLI(154) clears the recorded interrupts of the inputs from the designated
Interrupt Input Unit corresponding to ON bits in S. Once an interrupt is cleared,
the interrupt program will not be executed even if the interrupt is unmasked.
In the following example, CLI(154) is executed with S=00F2, so the recorded
interrupts for inputs 1, 4, 5, 6, and 7 are cleared. Recorded interrupts for inputs 0,
2, and 3 are unaffected.
Interrupt input 0
Interrupt input 1
Interrupt input 3
Memory status
Interrupt program execution
Interrupt program 3
CLI(154) used to clear interrupt 1
Interrupt program 0
Interrupt program 3
Ignored (interrupt already recorded)
0
1
3
Description
Interrupt Control Section 5-31