Omron SYSMAC CV Series - Page 525

Appendix AInstruction Set
515
Note Instructions marked with an asterisk (*) are supported by version-2 CVM1 CPUs only.
Alphabetic List of Instructions by Function Code
Sequence Control, Error Handling, and Step
Control Instructions
Code Mnemonic Name
000 NOP NO OPERATION
001 END END
002 IL INTERLOCK
003 ILC INTERLOCK CLEAR
004 JMP JUMP
005 JME JUMP END
006
FAL(j)
FAILURE ALARM
007 FALS FAILURE ALARM
008 STEP STEP DEFINE
009 SNXT STEP START
Sequence I/O Instructions
Code Mnemonic Name
010 NOT NOT
011 KEEP(!) KEEP
012 CNTR REVERSIBLE COUNTER
013 DIFU(!) DIFFERENTIATE UP
014 DIFD(!) DIFFERENTIATE DOWN
015 TIMH HIGH-SPEED TIMER
016
SET(!ji)
SET
017
RSET(!ji)
RSET
018 UP* CONDITION ON
019 DOWN* CONDITION OFF
Data Compare Instructions
Code Mnemonic Name
020
CMP(!j)
COMPARE
021 CMPL DOUBLE COMPARE
022
BCMP(j)
BLOCK COMPARE
023
TCMP(j)
TABLE COMPARE
024
MCMP(j)
MULTIPLE COMPARE
025
EQU(j)
EQUAL
026 CPS(!)* SIGNED BINARY
COMPARE
027 CPSL* DOUBLE SIGNED BINARY
COMPARE
028 CMP(!)* UNSIGNED COMPARE
029 CMPL* DOUBLE UNSIGNED
COMPARE
Data Move and Sequence Output Instructions
Code Mnemonic Name
030
MOV(!j)
MOVE
031
MVN(j)
MOVE NOT
032
MOVL(j)
DOUBLE MOVE
033
MVNL(j)
DOUBLE MOVE NOT
034
XCHG(j)
DATA EXCHANGE
035
XCGL(j)
DOUBLE DATA EXCHANGE
036
MOVR(j)
MOVE TO REGISTER
037 MOVQ MOVE QUICK
038
XFRB(j)*
MULTIPLE BIT TRANSFER
040
XFER(j)
BLOCK TRANSFER
041
BSET(j)
BLOCK SET
042
MOVB(j)
MOVE BIT
043
MOVD(j)
MOVE DIGIT
044
DIST(j)
SINGLE WORD
DISTRIBUTE
045
COLL(j)
DATA COLLECT
046
BXFR(j)*
INTERBANK BLOCK
TRANSFER
047
SETA(j)*
MULTIPLE BIT SET
048
RSTA(j)*
MULTIPLE BIT RESET