Abov MC97F60128 - Page 112

112
MC97F60128
ABOV Semiconductor Co., Ltd.
PADB (PA Debounce Enable Register): D7H
7
6
5
4
3
2
1
0
–
–
–
PA4DB
PA3DB
PA2DB
PA1DB
PA0DB
–
–
–
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
PA4DB
Configure Debounce of PA4 Port
0
Disable
1
Enable
PA3DB
Configure Debounce of PA3Port
0
Disable
1
Enable
PA2DB
Configure Debounce of PA2 Port
0
Disable
1
Enable
PA1DB
Configure Debounce of PA1 Port
0
Disable
1
Enable
PA0DB
Configure Debounce of PA0 Port
0
Disable
1
Enable
NOTE)
1. If the same level is not detected on enabled pin three or four times in a row at the sampling
clock, the signal is eliminated as noise.
2. A pulse level should be input for the duration of 3 clocks or more to be actually detected as a
valid edge.
3. The port debounce is automatically disabled at stop mode and recovered after stop mode
release.
4. Refer to the port 1 debounce enable register (P1DB) for the debounce clock of port A.