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Abov MC97F60128 User Manual

Abov MC97F60128
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MC97F60128
ABOV Semiconductor Co., Ltd.
13. RESET
13.1 Overview
The following is the hardware setting value.
On Chip Hardware
Initial Value
Program Counter (PC)
0000h
Accumulator
00h
Stack Pointer (SP)
07h
Peripheral Clock
On
Control Register
Refer to the Peripheral Registers
Table 13-1 Reset State
13.2 Reset Source
The MC97F60128 has five types of reset sources. The following is the reset sources.
− External RESETB
− Power ON RESET (POR)
− WDT Overflow Reset (In the case of WDTEN = `1`)
− Low Voltage Reset (In the case of LVREN = `0 `)
− Flash fail detection ( Parity Check )
− OCD Reset
13.3 RESET Block Diagram
Figure 13.1 RESET Block Diagram
WDT RST
WDT RSTEN
Ext RESET
Disable by FUSE
RESET Noise
Canceller
LVR
LVR Enable
RESET Noise
Canceller
POR RST
OCD RST
S Q
R
Internal
Reset
IFBIT
(BIT Overflow)
OCD RSTEN
FLASH FAIL
FFCHK Enable

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Abov MC97F60128 Specifications

General IconGeneral
BrandAbov
ModelMC97F60128
CategoryMicrocontrollers
LanguageEnglish

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