Abov MC97F60128 User Manual

142
MC97F60128
ABOV Semiconductor Co., Ltd.
11.1.4 Register Map
Name
Address
Dir
Default
Description
SCCR
8AH
R/W
00H
System and Clock Control Register
OSCCR
C8H
R/W
08H
Oscillator Control Register
PLLCR
D6H
R/W
00H
Phase Locked-Loop Control Register
Table 11-1 Clock Generator Register Map
11.1.5 Clock Generator Register Description
The clock generator register uses clock control for system operation. The clock generation consists of system and
clock control register, oscillator control register and phase locked-loop control register.
11.1.6 Register Description for Clock Generator
SCCR (System and Clock Control Register) : 8AH
7
6
5
4
3
2
1
0
–
PSAVE
–
–
–
–
SCLK1
SCLK0
–
R/W
–
–
–
–
R/W
R/W
Initial value : 00H
PSAVE
Power Save Mode Control Bit
0
Normal circuit for sub oscillator
1
Power saving circuit for sub oscillator
NOTE)
1. A capacitor (0.1μF) should be connected between VREG
and VSS when the sub oscillator is used to power saving
mode.
2. The PSAVE automatically cleared to ‘0’ when the sub
oscillator is stopped by SCLKE or CPU is entered into
STOP mode in sub operating mode.
3. The delay is needed 500ms over from sub osc start to
PSAVE change to “1”.
SCLK [1:0]
System Clock Selection Bit
SCLK1
SCLK0
Description
0
0
INT RC OSC (f
IRC
) for system clock
0
1
External Main OSC (f
XIN
) for system clock
1
0
External Sub OSC (f
SUB
) for system clock
1
1
Phase Locked-Loop (f
PLL
) for system clock

Abov MC97F60128 Specifications

General

Brand	Abov
Model	MC97F60128
Category	Microcontrollers
Language	English