Abov MC97F60128 - USI01 SPI Block Diagram

265
MC97F60128
ABOV Semiconductor Co., Ltd.
11.13.22 USI0/1 SPI Block Diagram
RXCIEn
Rx Control
Receive Shift Register
(RXSR)
Data
Recovery
DORn Checker USInDR[0], (Rx)
Tx Control
Transmit Shift Register
(TXSR)
USInDR, (Tx)
I
N
T
E
R
N
A
L
B
U
S
L
I
N
E
M
U
X
LOOPSn
TXCn
TXCIEn DRIEn
DREn
Empty signal
To interrupt
block
INT_ACK
Clear
RXCn
Baud Rate Generator
USInBD
TXEn
SCLK
(fx: System clock)
MISOn
MOSIn
M
U
X
MASTERn
D
E
P
FXCHn
SCKn
SCK
Control
MASTERn
RXEn
To interrupt
block
M
U
X
Edge Detector
And
Controller
SSn
SS
Control
CPHAnCPOLn
ORDn
(MSB/LSB-1st)
USInDR[1], (Rx)
USInSSEN
Figure 11.71 USI0/1 SPI Block Diagram (where n = 0 and 1)