207
ABOV Semiconductor Co., Ltd.
11.8.3 10-Bit PWM One-Shot Mode Without Auto-Enable
The 10-bit PWM one-shot mode without auto-enable is selected by PWMMD[1:0] bits set to “00b”. A 10-bit counter
register is increased by internal clock input on operation. When the PWMCNTH/PWMCNTL is identical to the
PWMADRH/PWMADRL, a match signal is generated, the PWMOUT pin is inverted and the counting is continued to
“3FFH”. If a valid falling edge signal comes from the TRIG pin during the counting, the counter will be cleared to “000H”
and the 10-bit PWM generator will be restarted. But if there is no a valid falling edge signal of the TRIG pin, an
overflow will be generated finally and the 10-bit PWM generator finishes operation with automatically clearing the
PWMEN bit.
X 1 2 4 2 3 0 0
PWM clock
Counter
PWMADRH/L
PWM Interrupt
PWMOUT
Match
- PWMOUT signal without auto-enable: "Start Low" (PWMPOL = 1b)
Set PWMEN
0
Clear and Start
3 0
4
Match
41
TRIG Input
0
0 < Tst < 2/fpwm
Tst
5 3FF
Don’t care
TRIG Signal
Figure 11.41 A Timing Chart of 10-bit PWM One-Shot Mode Without Auto-Enable
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