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Abov MC97F60128 User Manual

Abov MC97F60128
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MC97F60128
10.7 Multi Interrupt
If two requests of different priority levels are received simultaneously, the request of higher priority level is served first.
If more than one interrupt request are received, the interrupt polling sequence determines which request is served first
by hardware. However, for special features, multi-interrupt processing can be executed by software.
Figure 10.6 Effective Timing of Interrupt
Figure 10.6 shows an example of multi-interrupt processing. While INT1 is served, INT0 which has higher priority than
INT1 is occurred. Then INT0 is served immediately and then the remain part of INT1 service routine is executed. If the
priority level of INT0 is same or lower than INT1, INT0 will be served after the INT1 service has completed.
An interrupt service routine may be only interrupted by an interrupt of higher priority and, if two interrupts of different
priorityoccur at the same time, the higher level interrupt will be served first. An interrupt cannot be interrupted by
another interrupt ofthe same or a lower priority level. If two interrupts of the same priority level occur simultaneously,
the service order for those interrupts is determined by the scan order.
Main Program
Service
Occur
INT1 Interrupt
INT1 ISR
Occur
INT0 Interrupt
INT0 ISR
RETI
RETI
Set EA

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Abov MC97F60128 Specifications

General IconGeneral
BrandAbov
ModelMC97F60128
CategoryMicrocontrollers
LanguageEnglish

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