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ABOV Semiconductor Co., Ltd.
10. Interrupt Controller
10.1 Overview
The MC97F60128 supports up to 24 interrupt sources. The interrupts have separate enable register bits associated
with them, allowing software control. They can also have four levels of priority assigned to them. The non-maskable
interrupt source is always enabled with a higher priority than any other interrupt source and is not controllable by
software. The interrupt controller has following features:
− Receive the request from 24 interrupt source
− Individual priority
− 4 priority levels
− Multi Interrupt possibility
− If the requests of different priority levels are received simultaneously, the request of higher prioritylevel is
served first.
− Each interrupt source can be controlled by EA bit and each IEx bit
− Interrupt latency: 3~9 machinecycles in single interrupt system
The non-maskable interrupt is always enabled. The maskable interrupts are enabled through four pair of interrupt
enable registers (IE, IE1, IE2 and IE3). Each bit of IE, IE1, IE2, IE3 register individually enables/disables the
corresponding interrupt source. Overall control is provided by bit 7 of IE (EA). When EA is set to ‘0’, all interrupts are
disabled: when EA is set to ‘1’, interrupts are individually enabled or disabled through the other bits of the interrupt
enable registers. The EA bit is always cleared to ‘0’ jumping to an interrupt service vector and set to ‘1’ executing the
[RETI] instruction. The MC97F60128 supports a four-level priority scheme. Each maskable interrupt is individually
assigned to one of four priority levels according to IP0H/L, IP1H/L, IP2H/L and IP3H/L.
Default interrupt mode is level-trigger mode basically, but if needed, it is possible to change to edge-trigger mode.
Priority is set by two bits of interrupt priority registers (one bit from IPxH, another one from IPxL). Interrupt service
routine serves higher priority interrupt first. If two requests of different priority levels are received simultaneously, the
request of higher priority level is served prior to the lower one.
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