Abov MC97F60128 User Manual

253
MC97F60128
ABOV Semiconductor Co., Ltd.
11.13.3 USI0/1 UART Block Diagram
RXDn
Rx
Control
Clock
Recovery
Receive Shift Register
(RXSR)
Data
Recovery
DORn/PEn/FEn
Checker
USInDR[0], USInRX8[0], (Rx)
USInDR[1], USInRX8[1], (Rx)
TXDn
Tx
Control
Stop bit
Generator
Parity
Generator
Transmit Shift Register
(TXSR)
USInDR, USInTX8, (Tx)
USInP[1:0]
M
U
X
LOOPSn
TXCn
TXCIEn DRIEn
DREn
Empty signal
To interrupt
block
INT_ACK
Clear
RXCn
RXCIEnWAKEIEn
WAKEn
At Stop mode
To interrupt
block
SCLK
(fx: System clock)
Low level
detector
2
USInS[2:0]
3
USInS[2:0]
3
TXEn
RXEn
DBLSn
USInSB
Baud Rate Generator
USInBD
I
N
T
E
R
N
A
L
B
U
S
L
I
N
E
SCKn
ACK
Control
Clock
Sync Logic
Master
USInMS[1:0]
M
U
X
M
U
X
USInMS[1:0]
USInMS[1:0]
2
2
2
Figure 11.62 USI0/1 UART Block Diagram (Where n = 0 and 1)

Abov MC97F60128 Specifications

General

Brand	Abov
Model	MC97F60128
Category	Microcontrollers
Language	English