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ABOV Semiconductor Co., Ltd.
8. Memory
The MC97F60128 addresses two separate address memory stores: Program memory and Data memory. The logical
separation of Program and Data memory allows Data memory to be accessed by 8-bit addresses, which makes the 8-
bit CPU access the data memory more rapidly. Nevertheless, 16-bit Data memory addresses can also be generated
through the DPTR register.
Program Memory can be up to 64K bytes of Program memory in a bank. MC97F60128 provides on-chip 128 Kbytes
of the ISP type flash program memory, which can be read and written to. Internal data memory (IRAM) is 256 bytes
and it includes the stack area. External data memory (XRAM) is 8,192 bytes and it includes 64 bytes of LCD display
RAM.
8.1 Program Memory
A 16-bit program counter is capable of addressing up to 64 Kbytes for one bank of memory space, but this device has
128K bytes program memory space with bank selection scheme.
Figure 8.1 shows the map of the lower part of the program memory. After reset, the CPU begins execution from
location 0000H. Each interrupt is assigned a fixed location in program memory. The interrupt causes the CPU to jump
to that location, where it commences execution of the service routine. External interrupt 0-7, for example, is assigned
to location 002BH. If external interrupt 0-7 is going to be used, its service routine must begin at location 002BH. If the
interrupt is not going to be used, its service location is available as general purpose program memory. If an interrupt
service routine is short enough (as is often the case in control applications), it can reside entirely within that 8 bytes
interval. Longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other
interrupts are in use.
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