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ABOV Semiconductor Co., Ltd.
11.12.9 Parity Generator
The parity generator calculates the parity bit for the serial frame data to be sent. When parity bit is enabled
(UnPM[1]=1), the transmitter control logic inserts the parity bit between the MSB and the first stop bit of the frame to be
sent.
11.12.10 Disabling Transmitter
Disabling the transmitter by clearing the TXEn bit will not become effective until ongoing transmission is completed.
When the Transmitter is disabled, the TXDn pin can be used as a normal general purpose I/O (GPIO).
11.12.11 UART Receiver
The UART2/3/4 receiver is enabled by setting the RXEn bit in the UARTnCR2 register. When the receiver is enabled,
the RXDn pin should be set to the input port for the serial input pin of UART2/3/4 by P65IO/ P52IO/ P50IO bit. The
baud-rate, mode of operation and frame format must be set before serial reception.
11.12.12 Receiving Rx data
The receiver starts data reception when it detects a valid start bit (LOW) on RXDn pin. Each bit after start bit is
sampled at pre-defined baud-rate (asynchronous) and shifted into the receive shift register until the first stop bit of a
frame is received. Even if there’s 2
nd
stop bit in the frame, the 2
nd
stop bit is ignored by the receiver. That is, receiving
the first stop bit means that a complete serial frame is present in the receiver shift register and contents of the shift
register are to be moved into the receive buffer. The receive buffer is read by reading the UARTnDR register.
If 9-bit characters are used (UnSIZE[2:0] = “111”), the ninth bit is stored in the RX8n bit position in the UARTnCR3
register. The 9
th
bit must be read from the RX8n bit before reading the low 8 bits from the UARTnDR register. Likewise,
the error flags FEn, DORn, PEn must be read before reading the data from UARTnDR register. It’s because the error
flags are stored in the same FIFO position of the receive buffer.
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