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ABOV Semiconductor Co., Ltd.
11.13.8 USI0/1 UART Parity bit
The parity bit is calculated by doing an exclusive-OR of all the data bits. If odd parity is used, the result of the
exclusive-O is inverted. The parity bit is located between the MSB and first stop bit of a serial frame.
P
even
= D
n-1
^ … ^ D
3
^ D
2
^ D
1
^ D
0
^ 0
P
odd
= D
n-1
^ … ^ D
3
^ D
2
^ D
1
^ D
0
^ 1
P
even
: Parity bit using even parity
P
odd
: Parity bit using odd parity
D
n
: Data bit n of the character
11.13.9 USI0/1 UART Transmitter
The UART transmitter is enabled by setting the TXEn bit in USInCR2 register. When the Transmitter is enabled, the
TXDn pin should be set to TXDn function for the serial output pin of UART by the P3FSRL[3:2]/P5FSRH[4:3]. The
baud-rate, operation mode and frame format must be setup once before doing any transmission. In synchronous
operation mode, the SCKn pin is used as transmission clock, so it should be selected to do SCKn function by
P3FSRL[1:0]/P5FSRH[2:1].
11.13.10 USI0/1 UART Sending Tx data
A data transmission is initiated by loading the transmit buffer (USInDR register I/O location) with the data to be
transmitted. The data written in transmit buffer is moved to the shift register when the shift register is ready to send a
new frame. The shift register is loaded with the new data if it is in idle state or immediately after the last stop bit of the
previous frame is transmitted. When the shift register is loaded with new data, it will transfer one complete frame
according to the settings of control registers. If the 9-bit characters are used in asynchronous or synchronous
operation mode, the ninth bit must be written to the USInTX8 bit in USInCR3 register before it is loaded to the transmit
buffer (USInDR register).
11.13.11 USI0/1 UART Transmitter flag and interrupt
The UART transmitter has 2 flags which indicate its state. One is UART data register empty flag (DREn) and the other
is transmit complete flag (TXCn). Both flags can be interrupt sources.
DREn flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is
empty and cleared when the transmit buffer contains data to be transmitted but has not yet been moved into the shift
register. And also this flag can be cleared by writing ‘0’ to this bit position. Writing ‘1’ to this bit position is prevented.
When the data register empty interrupt enable (DRIEn) bit in USInCR2 register is set and the global interrupt is
enabled, USInST1 status register empty interrupt is generated while DREn flag is set.
The transmit complete (TXCn) flag bit is set when the entire frame in the transmit shift register has been shifted out
and there is no more data in the transmit buffer. The TXCn flag is automatically cleared when the transmit complete
interrupt service routine is executed or it can be cleared by writing ‘0’ to TXCn bit in USInST1 register.
When the transmit complete interrupt enable (TXCIEn) bit in USInCR2 register is set and the global interrupt is
enabled, UART transmit complete interrupt is generated while TXCn flag is set.
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