Abov MC97F60128 User Manual

324
MC97F60128
ABOV Semiconductor Co., Ltd.
11.17.6 Block Diagram
7-Bit Up-counter
Decoder Buffer
Decoder Data
(DECDR, R/W)
Clear
Match Signal
>>1
FIFO Empty Signal
FADPCM Result Signal
DODRH/L
(16-bits, Read only)
DMIFR
DFEIFR
FADPCM
Decoder block
Comparator
D_FIFO Data
(DFIFOR, R/W)
Data out[7:0]
D_FIFO
(8-bytes)
Data Request
Initialize
Bundle Data
(DBDLR, R/W)
M
U
X
fx/4
fx/8
fx/16
2
DCLKS[1:0]
fx/2
DCEN
DIVS
DECEN
DFFF
DMIE
DFEIE
To interrupt
block
Trigger
Generator/
Controller
DTRS
Voice Prompt Size
Decrement by ‘1’
(VPSIZE1/2/3 Registers)
VPSDEC
If match, ‘0’
Comparator
“0x000000"
2
ATRIGS[1:0]
2-bits
up counter
VPEDIE
To interrupt
block
VPEDIFR
OVF
Internal
Flag
If ‘1’, Clear signal
M
U
X
SPICSS
SPI2 Control Signal
From SPI2 Block
SPI3 Control Signal
From SPI3 Block
FIFO Empty Signal
Match Signal
SPI2DR (8-bit)
8
Command/Address
Write Controller
(SFCMD, VPADDR1/2/3)
7
SFDDNO
SFRDST
Tri-Signal 1
Tri-Signal 0
SPI3DR (8-bit)
SPICSS
Tri-Signal 0
ATRIGS[1:0]
Tri-Signal 2
VPTBLIE
To interrupt
block
VPTBLIFR
Address/Size/Inform Registers
(VPADDR1/2/3, VPSIZE1/2/3, VPINF1/2)
Receive Data
Allocator/Writer
Tri-Signal 0
Tri-Signal 1
Tri-Signal 2
2
Figure 11.103 Fine ADPCM Block Diagram

Abov MC97F60128 Specifications

General

Brand	Abov
Model	MC97F60128
Category	Microcontrollers
Language	English