Abov MC97F60128 User Manual

141
MC97F60128
ABOV Semiconductor Co., Ltd.
11.1.2 Block Diagram
Clock
Change
System
Clock Gen.
SCLK (fx)
(Core, System,
Peripheral)
DCLK
BIT
WDT
BIT
overflow
XIN
XOUT
Main OSC
fXIN
STOP Mode
XCLKE
WDTRC OSC
(5KHz)
WDTCK
Stabilization Time
Generation
M
U
X
WDT clock
SXIN
SXOUT
Sub OSC
fSUB
STOP Mode
SCLKE
WT
2
SCLK[1:0]
/256
Internal RC OSC
(16MHz)
STOP Mode
IRCE
PLL
fPLL
BIT clock
fx/4096
fx/1024
fx/128
fx/16
M
U
X
BITCK[1:0]
fIRC
1/2
1/4
1/8
M
U
X
1/16
1/32
3
IRCS[2:0]
Figure 11.1 Clock Generator Block Diagram
11.1.3 Phase Locked-Loop Block Diagram
Phase
Locked
Loop
Feedback Divider
fVCO÷(1500)
Post 2-Divider
fVCO÷2
P2DIV
P2DIV[1:0]
2
PLLEN
VCO
fVCO
fPLL
fFB
Post 1-Divider
fVCO÷(P1DIV+3)
P1DIV[1:0]
2
Figure 11.2 Phase Locked-Loop Circuit Diagram

Abov MC97F60128 Specifications

General

Brand	Abov
Model	MC97F60128
Category	Microcontrollers
Language	English