Abov MC97F60128 User Manual

155
MC97F60128
ABOV Semiconductor Co., Ltd.
11.5.2 8-Bit Timer/Counter Mode
The 8-bit timer/counter mode is selected by control register as shown in Figure 11.7.
The 8-bit timer have counter and data register. The counter register is increased by internal or external clock input.
Timer 0/1/2 can use the input clock with one of 2, 4, 8, 32, 128, 512 and 2048 prescaler division rates (TnCK[2:0]).
When the value of TnCNT and TnDR is identical in timer 0/1/2, a match signal is generated and the interrupt of Timer n
occurs. TnCNT value is automatically cleared by match signal. It can be also cleared by software (TnCC).
The external clock (ECn) counts up the timer at the rising edge. If the ECn is selected as a clock source by TnCK[2:0],
EC0/EC1/EC2 port should be set to the input port by P40IO/P41IO/P42IO bit.
P
r
e
s
c
a
l
e
r
fx
M
U
X
fx/2
TnCNT(8Bit)
ECn
fx/4
fx/8
fx/32
fx/128
fx/512
fx/2048
3
TnCK[2:0]
TnEN
8-bit Timer n Counter
TnDR(8Bit)
Comparator
TnO/PWMnO
8-bit Timer n Data Register
Match signal
Clear
Match
MUX
TnMS[1:0]
2
TnEN - TnMS1 TnMS0 TnCK2 TnCK1 TnCK0 TnCCTnCR
1 - 0 0 x x x x
ADDRESS : D2H/DAH/DDH
INITIAL VALUE: 0000_0000B
TnCC
TnIFR
To interrupt
block
TnMIE
S/W
Clear
Figure 11.7 8-Bit Timer/Counter Mode for Timer 0/1/2 (Where n = 0, 1 and 2)
Figure 11.8 8-Bit Timer/Counter 0/1/2 Example (Where n = 0, 1 and 2)
TnCNT
Value
Timer n
(TnIFR)
Interrupt
TIME
1
2
3
4
5
6
n-2
n-1
n
Interrupt Period
= P
CP
x (n+1)
0
Count Pulse Period
P
CP
Up-count
Match with TnDR
Occur
Interrupt
Occur
Interrupt
Occur
Interrupt

Abov MC97F60128 Specifications

General

Brand	Abov
Model	MC97F60128
Category	Microcontrollers
Language	English