Abov MC97F60128 - USI01 I2 C Block Diagram

276
MC97F60128
ABOV Semiconductor Co., Ltd.
11.13.34 USI0/1 I2C Block Diagram
Receive Shift Register
(RXSR)
Transmit Shift Register
(TXSR)
I
N
T
E
R
N
A
L
B
U
S
L
I
N
E
SCLK
(fx: System clock)
SDAn
SCLn
USInDR, (Rx)
VSS
N-ch
VSS
N-ch
SCL Out
Controller
SDA In/Out
Controller
SDA Hold Time Register
USInSDHR
SCL Low Period Register
USInSCLR
SCL High Period Register
USInSCHR
Time Generator
And
Time Controller
USInDR, (Tx)
Slave Address Register
USInSAR
General Call And
Address Detector
USInGCE
STOP/START
Condition Generator
STOPCn
STARTCn
ACK Signal
Generator
ACKnEN
RXACKn, GCALLn,
TENDn, STOPDn,
SSELn, MLOSTn,
BUSYn, TMODEn
Interrupt
Generator
To interrupt
block
IICnIFR
IICnIE
NOTE)
1. When the USI0/1 block is an I2C mode and the corresponding port is an sub-function for
SCLn/SDAn pin, The SCLn/SDAn pins are automatically set to the N-channel open-drain
outputs and the input latch is read in the case of reading the pins. The corresponding pull-
up resistor is determined by the control register.
Figure 11.78 USI0/1 I2C Block Diagram (where n = 0 and 1)