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Abov MC97F60128 - Features

Abov MC97F60128
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5
MC97F60128
ABOV Semiconductor Co., Ltd.
1.2 Features
CPU
8-Bit CISC Core (High Speed 8051 2 clocks per cycle)
ROM (FLASH) Capacity
128 Kbytes Flash with self read/write capability
On chip debug and In-System Programming(ISP)
Endurance : 10,000 times
Retention : 10 years
256 bytes IRAM
8,192 bytes XRAM
General Purpose I/O (GPIO)
Normal I/O : 20 Ports
(P0, P1[7:6], P6[5:1], P9)
LCD shared I/O : 68 Ports
(P1[5:0],P2, P3, P4, P5, P6[0], P7, P8,PA,PB, PD)
10Bit PWM Generator
Emergency/Shot stop available
Timer/ Counter
Basic Interval Timer (BIT) 8-bi 1-ch
Watch Dog Timer (WDT) 8-bi 1-ch
5kHz internal RC oscillator
8-Bit × 3ch (T0/T1/T2), 16-Bit × 4ch (T3/T4/T5/T6)
8-Bit × 2ch (T7/T8) or 16-Bit × 1ch (T7)
Programmable Pulse Generation
8-Bit PWM (by T0/T1/T2)
Pulse generation (by T3/T4/T5/T6)
6-ch 10-Bit PWM for Motor (by T8)
Watch Timer (WT)
3.91ms/0.25s/0.5s/1s /1 min interval at 32.768kHz
Buzzer
6-Bit × 1-ch
SPI
8-Bi 2-ch
UART
8-Bit UART × 3-ch
USI (UART + SPI + I2C)
8Bit UART × 2ch, 8Bit SPI × 2ch and I2C × 2ch
12-Bit A/D Converter
15 Input channels
12-Bit D/A Converter
1 output channel
FADPCM Decoder
Fine ADPCM decoder (32kbps @ fs=8kHz)
Adjustable sampling frequency and bundle size
Automatic access to external serial flash (16MB)
LCD Driver
60 Segments and 8 Common
1/2, 1/3, 1/4, 1/5, 1/6, 1/8 duty selectable
Resistor bias and 16-step contrast control
Automatic bias control
Power On Reset
Reset release level (1.4V)

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