Abov MC97F60128 - Block Diagram

237
MC97F60128
ABOV Semiconductor Co., Ltd.
11.12.2 Block Diagram
RXDn
Rx
Control
Clock
Recovery
Receive Shift Register
(RXSR)
Data
Recovery
DORn/PEn/FEn
Checker
UARTnDR[0]
(Rx)
UARTnDR[1]
(Rx)
TXDn
Tx
Control
Stop bit
Generator
M
U
X
UnPM1
Parity
Generator
Transmit Shift Register
(TXSR)
UARTnDR(Tx)
UnPM0
I
N
T
E
R
N
A
L
B
U
S
L
I
N
E
M
U
X
LOOPSn
TXCn
TXCIEn UDRIEn
UDREn
Empty signal
To interrupt
block
INT_ACK
Clear
RXCn
RXCIEnWAKEIEn
WAKEn
At Stop mode
To interrupt
block
Baud Rate Generator
UARTnBD
SCLK
Low level
detector
Figure 11.56 UART Block Diagram(where n = 2,3 and 4)