Abov MC97F60128 User Manual

150
MC97F60128
ABOV Semiconductor Co., Ltd.
11.3.6 Register Description for Watch Dog Timer
WDTCNT (Watch Dog Timer Counter Register: Read Case) : 8EH
7
6
5
4
3
2
1
0
WDTCNT7
WDTCNT6
WDTCNT5
WDTCNT4
WDTCNT3
WDTCNT2
WDTCNT1
WDTCNT0
R
R
R
R
R
R
R
R
Initial value : 00H
WDTCNT[7:0]
WDT Counter
WDTDR (Watch Dog Timer Data Register: Write Case) : 8EH
7
6
5
4
3
2
1
0
WDTDR7
WDTDR6
WDTDR5
WDTDR4
WDTDR3
WDTDR2
WDTDR1
WDTDR0
W
W
W
W
W
W
W
W
Initial value : FFH
WDTDR[7:0]
Set a period
WDT Interrupt Interval=(BIT Interrupt Interval) x(WDTDR Value+1)
NOTE)
1. Do not write “0” in the WDTDR register.
WDTCR (Watch Dog Timer Control Register) : 8DH
7
6
5
4
3
2
1
0
WDTEN
WDTRSON
WDTCL
WDTIE
–
–
WDTCK
WDTIFR
R/W
R/W
R/W
R/W
–
–
R/W
R/W
Initial value : 00H
WDTEN
Control WDT Operation
0
Disable
1
Enable
WDTRSON
Control WDT RESET Operation
0
Free Running 8-bit timer
1
Watch Dog Timer RESET ON
WDTIE
Enable or Disable Watch Dog Timer Interrupt
0
Disable
1
Enable
WDTCL
Clear WDT Counter
0
Free Run
1
Clear WDT Counter (auto clear after 1 Cycle)
WDTCK
Control WDT Clock Selection Bit
0
BIT overflow for WDT clock (WDTRC disable)
1
WDTRC for WDT clock (WDTRC enable)
WDTIFR
When WDT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit. So,
the flag should be cleared by software. Writing “1” has no effect.
0
WDT Interrupt no generation
1
WDT Interrupt generation

Abov MC97F60128 Specifications

General

Brand	Abov
Model	MC97F60128
Category	Microcontrollers
Language	English