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ABOV Semiconductor Co., Ltd.
2. An interrupt request is delayed during data are written to IE, IE1, IE2, IE3, IP0L/H, IP1L/H, IP2L/H,
IP3L/H and
PCON register..
10.4 Interrupt Vector Table
The interrupt controller supports 24 interrupt sources as shown in the Table 11-1. When interrupt is served, long call
instruction (LCALL) is executed and program counter jumps to the vector address. All interrupt requests have their
own priority order.
External Interrupt 0 – 7
SPI2 Rx FIFO Full Interrupt
T0/1/2 OVF/Match Interrupt
T7 Match Interrupt
T8 Interrupt
Emergency Stop Interrupt
FADPCM Decoder Interrupt
DAC Interrupt
External Interrupt 8/9/18
SPI2 Tx FIFO Empty Interrupt
WT Interrupt
PWM Generator Overflow Interrupt
Shot Stop Interrupt
TRIG Interrupt
EINTA – EINTJ Interrupt
BIT/WDT/ADC Interrupt
SP Overflow Interrupt
External Interrupt 10 – 17
Table 10-1 Interrupt Vector Address Table
For maskable interrupt execution, EA bit must set ‘1’ and specific interrupt must be enabled by writing ‘1’ to associated
bit in the IEx. If an interrupt request is received, the specific interrupt request flag is set to ‘1’. And it remains ‘1’ until
CPU accepts interrupt. If the interrupt is served, the interrupt request flag will be cleared automatically.
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