Abov MC97F60128 - PA Port; PA Port Description; Register Description for PA

111
MC97F60128
ABOV Semiconductor Co., Ltd.
9.13 PA Port
9.13.1 PA Port Description
PA is 5-bit I/O port. PA control registers consist of PA data register (PA), PA direction register (PAIO), debounce
enable register (PADB), PA pull-up resistor selection register (PAPU) and PA open-drain selection register (PAOD).
Refer to the port function selection registers for the PA function selection.
9.13.2 Register description for PA
PA (PA Data Register): A3H
7
6
5
4
3
2
1
0
–
–
–
PA4
PA3
PA2
PA1
PA0
–
–
–
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
PA[4:0]
I/O Data
PAIO (PA Direction Register): E1H
7
6
5
4
3
2
1
0
–
–
–
PA4IO
PA3IO
PA2IO
PA1IO
PA0IO
–
–
–
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
PAIO[4:0]
PA Data I/O Direction.
0
Input
1
Output
NOTE)
1. EINTF-EINTJ function possible when
input
PAPU (PA Pull-up Resistor Selection Register): AFH
7
6
5
4
3
2
1
0
–
–
–
PA4PU
PA3PU
PA2PU
PA1PU
PA0PU
–
–
–
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
PAPU[4:0]
Configure Pull-up Resistor of PA Port
0
Disable
1
Enable
PAOD (PA Open-drain Selection Register): 401AH (XSFR)
7
6
5
4
3
2
1
0
–
–
–
PA4OD
PA3OD
PA2OD
PA1OD
PA0OD
–
–
–
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
PAOD[4:0]
Configure Open-drain of PA Port
0
Push-pull output
1
Open-drain output