Abov MC97F60128 - Usi01 (Uart + Spi + I2 C); Overview

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MC97F60128
ABOV Semiconductor Co., Ltd.
11.13 USI0/1 (UART + SPI + I2C)
11.13.1 Overview
The USI0/1 consists of USI0/1 control register1/2/3/4, USI0/1 status register 1/2, USI0/1 baud-rate generation register,
USI0/1 data register, USI0/1 SDA hold time register, USI0/1 SCL high period register, USI0/1 SCL low period register
and USI0/1 slave address register (USInCR1, USInCR2, USInCR3, USInCR4, USInST1, USInST2, USInBD, USInDR,
USInSDHR, USInSCHR, USInSCLR, USInSAR).
The operation mode is selected by the operation mode of USI0/1 selection bits (USInMS[1:0]).
It has four operating modes:
− Asynchronous mode (UART)
− Synchronous mode
− SPI mode
− I2C mode