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ABOV Semiconductor Co., Ltd.
11.13.20 USI0/1 SPI Mode
The USI0/1 can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features.
− Full Duplex, Three-wire synchronous data transfer
− Mater and Slave Operation
− Supports all four SPI0 modes of operation (mode 0, 1, 2 and 3)
− Selectable LSB first or MSB first data transfer
− Double buffered transmit and receive
− Programmable transmit bit rate
When SPI mode is enabled (USInMS[1:0]=”11”), the slave select (SSn) pin becomes active LOW input in slave mode
operation or can be output in master mode operation if USInSSEN bit is set to ‘0’.
Note that during SPI mode of operation, the pin RXDn is renamed as MISOn and TXDn is renamed as MOSIn for
compatibility to other SPI devices.
11.13.21 USI0/1 SPI Clock Formats and Timing
To accommodate a wide variety if synchronus serial peripherals from different manufacturers, the USI0/1 has a clock
polarity bit (CPOLn) and a clock phase control bit (CPHAn) to select one of four clock formats for data transfers.
CPOLn selectively insert an inverter in series with the clock. CPHAn chooses between two different clock phase
relationships between the clock and data. Note that CPHAn and CPOLn bits in USInCR1 register have different
meanings according to the USInMS[1:0] bits which decides the operating mode of USI0/1.
Table below shows four combinations of CPOLn and CPHAn for SPI mode 0, 1, 2 and 3.
Table 11-23 CPOLn Functionality (where n = 0 and 1)
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