127
ABOV Semiconductor Co., Ltd.
10.12.3 External Interrupt Flag Register (EIFLAG0, EIFLAG1)
The external interrupt flag 0 register (EIFLAG0) and external interrupt flag 1 register (EIFLAG1) areset to ‘1’ when the
external interrupt generating condition is satisfied. The flag is cleared when the interrupt service routine is executed.
Alternatively, the flag can be cleared by writing ‘0’ to it.
10.12.4 External Interrupt Polarity Register (EIPOL0L, EIPOL0H, EIPOL1)
The external interrupt polarity0 high/low register (EIPOL0H/L) and external interrupt polarity1 register
(EIPOL1)determines which type of rising/falling/both edge interrupt. Initially, default value is no interrupt at any edge.
10.12.5 Register Map
Interrupt Enable Register
Interrupt Enable Register 1
Interrupt Enable Register 2
Interrupt Enable Register 3
Interrupt Priority 0 Low Register
Interrupt Priority 0 High Register
Interrupt Priority 1 Low Register
Interrupt Priority 1 High Register
Interrupt Priority 2 Low Register
Interrupt Priority 2 High Register
Interrupt Priority 3 Low Register
Interrupt Priority 3 High Register
External Interrupt Flag 0 Register
External Interrupt Polarity 0 Low Register
External Interrupt Polarity 0 High Register
External Interrupt Flag 1 Register
External Interrupt Polarity 1 Register
External Interrupt Flag 2 Register
External Interrupt Polarity 2 Low Register
External Interrupt Polarity 2 High Register
External Interrupt Flag 3 Register
External Interrupt Polarity 3 Low Register
External Interrupt Polarity 3 High Register
External Interrupt Flag 4 Register
External Interrupt Polarity 4 Low Register
External Interrupt Polarity 4 High Register
Table 10-2 Interrupt Register Map