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ABOV Semiconductor Co., Ltd.
11.13.23 USI0/1 I2C Mode
The USI0/1 can be set to operate in industrial standard serial communicatin protocols mode. The I2C mode uses 2
bus lines serial data line (SDAn) and serial clock line (SCLn) to exchange data. Because both SDAn and SCLn lines
are open-drain output, each line needs pull-up resistor. The features are as shown below.
− Compatible with I2C bus standard
− Multi-master operation
− Up to 400kHz data transfer read speed
− 7 bit address
− Both master and slave operation
− Bus busy detection
11.13.24 USI0/1 I2C Bit Transfer
The data on the SDAn line must be stable during HIGH period of the clock, SCLn. The HIGH or LOW state of the data
line can only change when the clock signal on the SCLn line is LOW. The exceptions are START(S), repeated
START(Sr) and STOP(P) condition where data line changes when clock line is high.
Figure 11.72 Bit Transfer on the I2C-Bus (USIn, where n = 0 and 1)
Data line Stable:
Data valid
except S, Sr, P
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