Abov MC97F60128 User Manual

212
MC97F60128
ABOV Semiconductor Co., Ltd.
11.8.7 Block Diagram
PWMCC
Comparator
10-bit Counter
PWMCNTH/PWMCNTL
Clear
Match
Pulse
Generator
PWMOUT
R
P
r
e
s
c
a
l
e
r
fx
M
U
X
fx/4
fx/8
fx/32
fx/128
fx/16
fx/2
fx/1
PWMCK[2:0]
3
fx/64
Overflow
PWMEN
PWMEN
Clear
10-bit B Data Register
PWMBDRH/PWMBDRL
10-bit A Data Register
PWMADRH/PWMADRL
Delay Data Register
PWMDLYDR
PWMMD[1:0]
PWMPOL
TRIGRS[1:0]
2
Delay Controller
Set
2
EMGIFR
Noise Filter
Controller
Noise Filter
Data Register
NFILDR
TRIG
TRIGRS1
Shot Stop
Controller
EXTSP0
EXTSP1
EXTSP2
ESP0S[1:0]
ESP1S[1:0]
ESP2S[1:0]
Emergency Stop
Controller
2
2
2
SHTIFR
To interrupt
block
SHTIE
S/W
Clear
EMGIFR
To interrupt
block
EMGIE
S/W
Clear
POVIFR
To interrupt
block
POVIE
S/W
Clear
TRGIFR
To interrupt
block
TRGIE
S/W
Clear
NOTE)
1. The PWMEN bit is automatically cleared to “0b” after an overflow of the 10-bit counter
occurs at a PWM one-shot mode.
2. The PWMEN bit is set to “1b” by a falling edge trigger of the external TRIG pin when it is
a PWM one-shot mode with auto-enable and the EMGIFR bit is set to “0b”.
3. The noise filter controller has a timer to realize an invalid trigger signal. The timer will be
cleared and restarted every the new cycle of the PWM generator.
4. The noise filter controller doesn’t work if the noise filter data register (NFILDR) is “00H”.
5. If a shot stop occurs by a falling edge trigger of the selected pin, the PWMOUT pin goes to
low/high level according to PWMPOL = “0b”/”1b” during the remaining current PWM cycle,
respectively. After that, the next PWM cycle starts with the PWMBDR.
Figure 11.48 10-Bit PWM generator Block Diagram

Abov MC97F60128 Specifications

General

Brand	Abov
Model	MC97F60128
Category	Microcontrollers
Language	English