Abov MC97F60128 - Page 144

144
MC97F60128
ABOV Semiconductor Co., Ltd.
PLLCR (Phase Locked-Loop Control Register) : D6H
7
6
5
4
3
2
1
0
–
–
PLLSTA
P1DIV1
P1DIV0
P2DIV1
P2DIV0
PLLEN
–
–
R
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
PLLSTA
PLL Locked/Unlocked Status Bit
0
PLL currently in unlocked state
1
PLL currently in locked state
P1DIV[1:0]
PLL Post 1-Divider Selection Bits (49.152MHz)
P1DIV1
P1DIV0
Description
0
0
f
VCO
/3 = 16.384MHz
0
1
f
VCO
/4 = 12.888MHz
1
0
f
VCO
/5 = 9.8304MHz
1
1
f
VCO
/6 = 8.192MHz
P2DIV[1:0]
PLL Post 2-Divider Data Bits
P2DIV1
P2DIV0
Description
0
x
f
PLL
= f
VCO
/2
1
0
f
PLL
= f
VCO
/4
1
1
f
PLL
= f
VCO
/8
PLLEN
PLL Enable/Disable Control Bit
0
PLL Disable
1
PLL Enable