Abov MC97F60128 User Manual

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MC97F60128
ABOV Semiconductor Co., Ltd.
SPI3SR (SPI 3 Status Register) : 400FH (XSFR)
7
6
5
4
3
2
1
0
SPI3IFR
WCOL3
SS_HIGH3
–
FXCH3
SPI3SSEN
–
–
R/W
R
R/W
–
R/W
R/W
–
–
Initial value : 00H
SPI3IFR
When SPI 3 Interrupt occurs, this bit becomes ‘1’. IF SPI 3 interrupt is enable, this bit is
auto cleared by INT_ACK signal. And if SPI 3 Interrupt is disable, this bit is cleared
when the status register SP3ISR is read and then access (read/write) the data register
SPI3DR. Write ‘1’ has no effect.
0
SPI 3 Interrupt no generation
1
SPI 3 Interrupt generation
WCOL3
This bit is set if any data are written to the data register SPI3DR during transfer. This bit
is cleared when the status register SPI3SR is read and then access (read/write) the data
register SPI3DR
0
No collision
1
Collision
SS_HIGH3
When the SS3 pin is configured as input, if “HIGH” signal comes into the pin, this flag bit
will be set.
0
Cleared when ‘0’ is written
1
No effect when ‘1’ is written
FXCH3
SPI 3 port function exchange control bit.
0
No effect
1
Exchange MOSI3 and MISO3 function
SPI3SSEN
This bit controls the SS3 pin operation
0
Disable
1
Enable (The corresponding pin should be a normal input)

Abov MC97F60128 Specifications

General

Brand	Abov
Model	MC97F60128
Category	Microcontrollers
Language	English