Abov MC97F60128 User Manual

301
MC97F60128
ABOV Semiconductor Co., Ltd.
DACCR (D/A Converter Control Register) : 40C0H (XSFR)
7
6
5
4
3
2
1
0
DACIE
DACIFR
ADATID
DACBC
FADFEN
DACRLDS1
DACRLDS0
DACEN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
DACIE
Enable or Disable D/AC Interrupt
0
Disable
1
Enable
DACIFR
When D/AC Interrupt occurs, this bit becomes ‘1’. The flag is cleared only by writing a
‘0’ to the bit. So, the flag should be cleared by software. This interrupt is for a result that
the DACDRH register automatically increments to “800xH” or decrements to “000xH”.
Write ‘1’ has no effect.
0
D/AC interrupt no generation
1
D/AC interrupt generation
ADATID
Automatically D/A Converter Data Increment/Decrement
0
Disable automatically D/AC data increment/decrement
1
Automatically D/AC data increment from DACDR value to “800xH” when
DACEN bit is changed to “1b”.
Automatically D/AC data decrement from DACDR value to “000xH” when
DACEN bit is changed to “0b”.
NOTE)
1. It doesn’t fetch data from FADPCM block during
automatically data increment/decrement even if the
FADFEN bit is ‘1’.
DACBC
D/A Converter Buffer Clear
0
No effect
1
Clear the D/AC buffer (When write, automatically cleared to ‘0’ after being
cleared)
FADFEN
Decoder Result Output Data Fetch Enable
0
Disable to fetch data from FADPCM decoder block
1
Enable to fetch data from FADPCM decoder block
DACRLDS[1:0]
D/A Converter Reload Selection. These bits select a reload signal to load data from
D/AC data register to buffer.
DACRLDS1
DACRLDS0
Description
0
0
Always
0
1
FADPCM decoder match signal
1
0
Timer 0 match signal
1
1
Timer 1 match signal
DACEN
D/A Converter Enable Bit
0
Stop D/AC operation (Low level output)
1
Start D/AC operation

Abov MC97F60128 Specifications

General

Brand	Abov
Model	MC97F60128
Category	Microcontrollers
Language	English