Abov MC97F60128 - Page 81

81
MC97F60128
ABOV Semiconductor Co., Ltd.
P0DB (P0 Debounce Enable Register): CCH
7
6
5
4
3
2
1
0
P07DB
P06DB
P05DB
P04DB
P03DB
P02DB
P01DB
P00DB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
P07DB
Configure Debounce of P07 Port
0
Disable
1
Enable
P06DB
Configure Debounce of P06 Port
0
Disable
1
Enable
P05DB
Configure Debounce of P05 Port
0
Disable
1
Enable
P04DB
Configure Debounce of P04 Port
0
Disable
1
Enable
P03DB
Configure Debounce of P03Port
0
Disable
1
Enable
P02DB
Configure Debounce of P02 Port
0
Disable
1
Enable
P01DB
Configure Debounce of P01 Port
0
Disable
1
Enable
P00DB
Configure Debounce of P00 Port
0
Disable
1
Enable
NOTE)
1. If the same level is not detected on enabled pin three or four times in a row at the sampling
clock, the signal is eliminated as noise.
2. A pulse level should be input for the duration of 3 clocks or more to be actually detected as a
valid edge.
3. The port debounce is automatically disabled at stop mode and recovered after stop mode
release.
4. Refer to the port 1 debounce enable register (P1DB) for the debounce clock of port 0.