Abov MC97F60128 - Page 84

84
MC97F60128
ABOV Semiconductor Co., Ltd.
P1DB (P1 Debounce Enable Register): CDH
7
6
5
4
3
2
1
0
DBCLK1
DBCLK0
P15DB
P14DB
P13DB
P12DB
P11DB
P10DB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
DBCLK
Configure Debounce Clock of Port
DBCLK1
DBCLK0
description
0
0
fx
0
1
fx/4
1
0
fx/4096
1
1
fSUB (External sub OSC)
P15DB
Configure Debounce of P15Port
0
Disable
1
Enable
P14DB
Configure Debounce of P14 Port
0
Disable
1
Enable
P13DB
Configure Debounce of P13 Port
0
Disable
1
Enable
P12DB
Configure Debounce of P12 Port
0
Disable
1
Enable
P11DB
Configure Debounce of P11 Port
0
Disable
1
Enable
P10DB
Configure Debounce of P10 Port
0
Disable
1
Enable
NOTE)
1. If the same level is not detected on enabled pin three or four times in a row at the sampling
clock, the signal is eliminated as noise.
2. A pulse level should be input for the duration of 3 clock or more to be actually detected as a
valid edge.
3. The port debounce is automatically disabled at stop mode and recovered after stop mode
release.