Abov MC97F60128 - Page 94

94
MC97F60128
ABOV Semiconductor Co., Ltd.
P46DB (P4/P6 Debounce Enable Register): CEH
7
6
5
4
3
2
1
0
–
–
–
P62DB
P61DB
P45DB
P44DB
P43DB
–
–
–
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
P62DB
Configure Debounce of P62 Port
0
Disable
1
Enable
P61DB
Configure Debounce of P61 Port
0
Disable
1
Enable
P45DB
Configure Debounce of P45 Port
0
Disable
1
Enable
P44DB
Configure Debounce of P44 Port
0
Disable
1
Enable
P43DB
Configure Debounce of P43 Port
0
Disable
1
Enable
NOTE)
1. If the same level is not detected on enabled pin three or four times in a row at the sampling
clock, the signal is eliminated as noise.
2. A pulse level should be input for the duration of 3 clock or more to be actually detected as a
valid edge.
3. The port debounce is automatically disabled at stop mode and recovered after stop mode
release.
4. Refer to the port 1 debounce enable register (P1DB) for the debounce clock of port 4 and 6.