Agilent Technologies 93000 SOC Series User Manual

Lesson 1 – Analog Modules
81
20MHz Digitizer
The following figure shows the block diagram of the 20MHz
Digitizer (WDE); the bold lines show the single-ended input routes
of the WDE.
The WDE is a single-slot analog module installed in the testhead,
and has two identical digitizers that share the sequencer, trigger
and timing system. As shown in the following figure, the
sequencer, the SYNC CLK pin (which is the trigger input pin) and
the timing generator are shared between its two digitizers.
Each digitizer (called a digitizer core) has the own waveform
memory. Thus, two digitizer cores can capture two analog signals
with a very tight timing skew (±1 ns characteristics if filter is
through and input range is same for both digitizer cores) for multi-
site test, IQ baseband signal measurement and so on.
Block Diagram of WDE (Single-ended Input Routes)
Bandwidth Resolution Sampling Rate Waveform Memory
20 MHz 16 bits 125 ksps to 5 Msps 1 M samples (per digitizer core)
Pogo Pin
Input Multiplexer
A+ (16/Mode1)
D+ (10/Mode4)
C+ (12/Mode3)
B+ (14/Mode2)
DGND
Master Clock
Seq Start / CCLK Stop
SYNC CLK (04)
SYNC DATA (03)
Timing
Generator
C– (11/Mode7)
D– (09/Mode8)
A– (15/Mode5)
B– (13/Mode6)
AGND
Conversion Clock
(GND for SYNC CLK)
Core 1
Filter
ADC
Input
Amp
R1
R2
R1
Core 2
Filter
ADC
Input
Amp
R1
R2
R1
Waveform
Memory 1
Waveform
Memory 2
AGND
Offset DAC
Offset DAC
R1: 50 ohm or 1 Mohm
R2: used for differential input route
Sequencer

Agilent Technologies 93000 SOC Series Specifications

General

Brand	Agilent Technologies
Model	93000 SOC Series
Category	Test Equipment
Language	English