118
8331B–AVR–03/12
Atmel AVR XMEGA AU
Figure 9-6. Watchdog reset.
For information on configuration and use of the WDT, refer to the ”WDT – Watchdog Timer” on
page 128.
9.4.5 Software Reset
The software reset makes it possible to issue a system reset from software by writing to the soft-
ware reset bit in the reset control register.The reset will be issued within two CPU clock cycles
after writing the bit. It is not possible to execute any instruction from when a software reset is
requested until it is issued.
Figure 9-7. Software reset.
9.4.6 Program and Debug Interface Reset
The program and debug interface reset contains a separate reset source that is used to reset
the device during external programming and debugging. This reset source is accessible only
from external debuggers and programmers.
1-2 2MHz
CC
Cycles
SOFTWARE
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