Atmel AVR XMEGA AU series - Page 506

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8331B–AVR–03/12
Atmel AVR XMEGA AU
19.4 Register Summary .........................................................................................234
19.5 Interrupt Vector Summary .............................................................................234
20 USB – Universal Serial Bus Interface ................................................. 235
20.1 Features ........................................................................................................235
20.2 Overview ........................................................................................................235
20.3 Operation .......................................................................................................237
20.4 SRAM Memory Mapping ...............................................................................240
20.5 Clock Generation ...........................................................................................241
20.6 Ping-pong Operation .....................................................................................242
20.7 Multipacket Transfers ....................................................................................243
20.8 Auto Zero Length Packet ...............................................................................244
20.9 Transaction Complete FIFO ..........................................................................244
20.10 Interrupts and Events ....................................................................................245
20.11 VBUS Detection .............................................................................................247
20.12 On-chip Debug ..............................................................................................247
20.13 Register Description – USB ...........................................................................248
20.14 Register Description – USB Endpoint ............................................................255
20.15 Register Description – Frame ........................................................................260
20.16 Register Summary – USB Module .................................................................261
20.17 Register Summary – USB Endpoint ..............................................................261
20.18 Register Summary – Frame ..........................................................................261
20.19 USB Interrupt Vector Summary .....................................................................261
21 TWI – Two-Wire Interface .................................................................... 262
21.1 Features ........................................................................................................262
21.2 Overview ........................................................................................................262
21.3 General TWI Bus Concepts ...........................................................................263
21.4 TWI Bus State Logic ......................................................................................268
21.5 TWI Master Operation ...................................................................................269
21.6 TWI Slave Operation .....................................................................................271
21.7 Enabling External Driver Interface .................................................................273
21.8 Register Description – TWI ............................................................................274
21.9 Register Description – TWI Master ................................................................275
21.10 Register Description – TWI Slave ..................................................................280
21.11 Register Summary - TWI ...............................................................................286
21.12 Register Summary - TWI Master ...................................................................286