67
8331B–AVR–03/12
Atmel AVR XMEGA AU
Note: 1. CC channel C and D triggers are available only for timer/counters 0.
The group configuration is the “base_offset;” for example, TCC1_CCA for the timer/counter C1
CC channel A the transfer trigger.
5.14.5 TRFCNTL – Channel Block Transfer Count register L
The TRFCNTH and TRFCNTL register pair represents the 16-bit value TRFCNT. TRFCNT
defines the number of bytes in a block transfer. The value of TRFCNT is decremented after each
byte read by the DMA channel. When TRFCNT reaches zero, the register is reloaded with the
last value written to it.
• Bit 7:0 – TRFCNT[7:0]: Channel n Block Transfer Count register Low
These bits hold the LSB of the 16-bit block transfer count.
The default value of this register is 0x1. If a user writes 0x0 to this register and fires a DMA trig-
ger, DMA will be doing 0xFFFF transfers.
5.14.6 TRFCNTH – Channel Block Transfer Count register H
Reading and writing 16-bit values requires special attention. For details, refer to ”Accessing 16-
bit Registers” on page 13.
Table 5-12. DMA trigger source offset values for timer/ counter triggers.
TRGSRC Offset Value Group Configuration Description
+0x00 OVF Overflow/underflow
+0x01 ERR Error
+0x02 CCA Compare or capture channel A
+0x03 CCB Compare or capture channel B
+0x04 CCC
(1)
Compare or capture channel C
+0x05 CCD
(1)
Compare or capture channel D
Table 5-13. DMA trigger source offset values for USART triggers.
TRGSRC Offset Value Group Configuration Description
0x00 RXC Receive complete
0x01 DRE Data register empty
Bit 76543210
+0x04 TRFCNT[7:0] TRFCNTL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
+0x05 TRFCNT[15:8] TRFCNTH
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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