CHAPTER 3 THEORY OF OPERATION
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1.3.9 Reset circuit
The reset IC is a R3112N281C. The reset voltage is 2.8V (typ.) and the LOW period of reset is
22.4ms (typ.)
Fig. 3-11
1.3.10 Engine I/O
The interface with the engine PCB is by full-duplex synchronous serial method, of which
transfer rate is 520kbps.
Fig. 3-12
1.3.11 Panel I/O
The interface with the panel PCB is by full-duplex synchronous serial method.
Fig. 3-13
1.3.12 Video I/O
The video signal output from the ASIC is reversed through a transistor and output after being
corrected by the buffer IC.
Fig. 3-14
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