Cypress PSoC 4000 Series - 16. Timer, Counter, and PWM; 16.1 Features

PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 101
16. Timer, Counter, and PWM
The Timer, Counter, and Pulse Width Modulator (TCPWM) block in PSoC
®
4 implements the 16-bit timer, counter, pulse width
modulator (PWM), and quadrature decoder functionality. The block can be used to measure the period and pulse width of an
input signal (timer), find the number of times a particular event occurs (counter), generate PWM signals, or decode quadra-
ture signals. This chapter explains the features, implementation, and operational modes of the TCPWM block.
16.1 Features
■ One 16-bit timer, counter, or pulse width modulator (PWM)
■ The TCPWM block supports the following operational modes:
❐ Timer
❐ Capture
❐ Quadrature decoding
❐ Pulse width modulation
❐ Pseudo-random PWM
❐ PWM with dead time
■ Multiple counting modes – up, down, and up/down
■ Clock prescaling (division by 1, 2, 4, ... 64, 128)
■ Double buffering of compare/capture and period values
■ Supports interrupt on:
❐ Terminal Count – The final value in the counter register is reached
❐ Capture/Compare – The count is captured to the capture/compare register or the counter value equals the compare
value
■ Underflow, overflow, and capture/compare output signals that can be routed to dedicated GPIOs
■ Complementary line output for PWMs
■ Selectable start, reload, stop, count, and capture event signals for the TCPWM from the dedicated GPIOs with rising
edge, falling edge, both edges, and level trigger options
16.2 Block Diagram
Figure 16-1. TCPWM Block Diagram
Bus Interface
Underflow,
Overflow,
Capture/compare
Interrupt
line_out,
line_compl_out
System
Interface
Trigger_in
[4:0]
5
Counter
Trigger
Synchronization
Configuration
Registers
Bus Interface Logic
23
CPU Subsystem