Cypress PSoC 4000 Series - 15. Inter-Integrated Circuit (I2 C); 15.1 Features

PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 83
15. Inter-Integrated Circuit (I2C)
PSoC 4 contains a Serial Communication Block (SCB) configured to operate as a fixed-function I2C block. This section
explains the I
2
C implementation in PSoC. For more information on the I
2
C protocol specification, refer to the I
2
C-bus specifi-
cation available on the NXP website.
15.1 Features
This block supports the following features:
■ Master, slave, and master/slave mode
■ Slow-mode (50 kbps), standard-mode (100 kbps), and fast-mode (400 kbps)data-rates
■ 7- or 10-bit slave addressing (10-bit addressing requires firmware support)
■ Clock stretching and collision detection
■ Programmable oversampling of I
2
C clock signal (SCL)
■ Error reduction using an digital median filter on the input path of the I
2
C data signal (SDA)
■ Glitch-free signal transmission with an analog glitch filter
■ Interrupt or polling CPU interface
15.2 General Description
Figure 15-1 illustrates an example of an I
2
C communication network.
Figure 15-1. I
2
C Interface Block Diagram
The standard I
2
C bus is a two wire interface with the following lines:
■ Serial Data (SDA)
■ Serial Clock (SCL)
I
2
C devices are connected to these lines using open collector or open-drain output stages, with pull-up resistors (Rp). A sim-
ple master/slave relationship exists between devices. Masters and slaves can operate as either transmitter or receiver. Each
slave device connected to the bus is software addressable by a unique 7-bit address. PSoC also supports 10-bit address
matching for I
2
C with firmware support.
VDD
Rp
Rp
SCL
SDA
I2C
Master
I2C Slave I2C Slave I2C Slave