PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 147
19. Nonvolatile Memory Programming
Nonvolatile memory programming refers to the programming of flash memory in the PSoC
®
4 device. This chapter explains
the different functions that are part of device programming, such as erase, write, program, and checksum calculation.
Cypress-supplied programmers and other third-party programmers can use these functions to program the PSoC 4 device
with the data in an application hex file. They can also be used to perform bootload operations where the CPU will update a
portion of the flash memory.
19.1 Features
■ Supports programming through the debug and access port (DAP) and Cortex-M0 CPU
■ Supports both blocking and non-blocking flash program and erase operations from the Cortex-M0 CPU
19.2 Functional Description
Flash programming operations are implemented as system calls. System calls are executed out of SROM in the privileged
mode of operation. The user has no access to read or modify the SROM code. The DAP or the CM0 CPU requests the sys-
tem call by writing the function opcode and parameters to the System Performance Controller Interface (SPCIF) input regis-
ters, and then requesting the SROM to execute the function. Based on the function opcode, the System Performance
Controller (SPC) executes the corresponding system call from SROM and updates the SPCIF status register. The DAP or the
CPU should read this status register for the pass/fail result of the function execution. As part of function execution, the code in
SROM interacts with the SPCIF to do the actual flash programming operations.
PSoC 4 flash is programmed using a Program Erase Program (PEP) sequence. The flash cells are all programmed to a
known state, erased, and then the selected bits are programmed. This sequence increases the life of the flash by balancing
the stored charge. When writing to flash the data is first copied to a page latch buffer. The flash write functions are then used
to transfer this data to flash.
External programmers program the flash memory in PSoC 4 using the SWD protocol by sending the commands to the Debug
and Access Port (DAP). The programming sequence for the PSoC 4 device with an external programmer is given in the
PSoC 4000 Programming Specifications. Flash memory can also be programmed by the CM0 CPU by accessing the relevant
registers through the AHB interface. This type of programming is typically used to update a portion of the flash memory as
part of a bootload operation, or other application requirements, such as updating a lookup table stored in the flash memory.
All write operations to flash memory, whether from the DAP or from the CPU, are done through the SPCIF.
Note It can take as much as 20 milliseconds to write to flash. During this time, the device should not be reset, or unexpected
changes may be made to portions of the flash. Reset sources (see the Reset System chapter on page 77) include XRES pin,
software reset, and watchdog; make sure that these are not inadvertently activated. In addition, the low-voltage detect circuits
should be configured to generate an interrupt instead of a reset.
Note PSoC 4 implements a User Supervisory Flash (SFlash), which can be used to store application-specific information.
These rows are not part of the hex file; their programming is optional.
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