Cypress PSoC 4000 Series - 17.4 CapSense CSD Sensing

PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 129
CapSense
17.4 CapSense CSD Sensing
Figure 17-3 shows the block diagram of the PSoC 4 CapSense hardware.
Figure 17-3. PSoC 4 CapSense CSD Sensing
17.4.1 GPIO Cell Capacitance to Current
Converter
In the CapSense CSD system, the GPIO cells are config-
ured as switched capacitance circuits, which convert the
sensor capacitance to equivalent currents. Figure 17-4
shows a simplified diagram of the PSoC 4 GPIO cell struc-
ture.
PSoC 4 has two analog multiplexer buses: AMUXBUS A is
used for CSD sensing and AMUXBUS B is used for CSD
shielding. The GPIO switched capacitance circuit has two
possible configurations: source current to AMUXBUS A or
sink current from AMUXBUS A. Figure 17-5 shows the
switched capacitance configuration for sourcing current to
AMUXBUS A.
Figure 17-4. PSoC 4 GPIO Cell
GPIO
cell
GPIO
cell
GPIO
cell
8 bit IDAC
7 bit IDAC
GPIO pin
GPIO pin
GPIO pin
C
MOD
pin
V
REF
(1.2V)
C
S1
C
S2
C
SN
Integrating capacitor for
sigma-delta converter
C
MOD
IO cells configured as switched
capacitance circuits for capacitance
to current conversion
raw
counts
current to digital converter
AMUXBUS A forms an analog
multiplexer for the sensors
sensor 1
sensor 2
sensor N
IDAC
control
modulation clock
switching clock for
GPIO switched capacitance
circuits, frequency F
SW
frequency F
MOD
sigma-delta
converter
counter
sense
comparator
CapSense
clock generator
switching clock
modulation clock
(Both from
system
resources)
GPIO
Pin
V
DDD
AMUXBUS
A
AMUXBUS
B
SW
1
SW
2
SW
3
SW
4