Cypress PSoC 4000 Series - Power Modes

PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 105
Timer, Counter, and PWM
16.2.4.3 Outputs
The TCPWM has two outputs, line_out and line_compl_out (complementary of line_out). Note that the OV, UN, and CC con-
ditions can be used to drive line_out and line_compl_out if needed, by configuring the TCPWM_CNT_TR_CTRL2 register
(Table 16-3). The line_out and line_compl_out is enabled by the line_out_en and line_compl_out_en, one for each counter.
16.2.5 Power Modes
The TCPWM block works in Active and Sleep modes. The TCPWM block is powered from V
CCD
. The configuration registers
and other logic are powered in Deep-Sleep mode to keep the states of configuration registers. See Table 16-4 for details.
Table 16-3. Configuring Output Line for OV, UN, and CC Conditions
Field Bit Value Event Description
CC_MATCH_MODE
Default Value = 3
1:0
0 Set line_out to '1
Configures output line on a compare
match (CC) event
1 Clear line_out to '0
2 Invert line_out
3No change
OVERFLOW_MODE
Default Value = 3
3:2
0 Set line_out to '1
Configures output line on a overflow
(OV) event
1 Clear line_out to '0
2 Invert line_out
3No change
UNDERFLOW_MODE
Default Value = 3
5:4
0 Set line_out to '1
Configures output line on a underflow
(UN) event
1 Clear line_out to '0
2 Invert line_out
3No change
Table 16-4. Power Modes in TCPWM Block
Power Mode Block Status
Active This block is fully operational in this mode with clock running and power switched on.
Sleep All counter clocks are on, but bus interface cannot be accessed.
Deep-Sleep
In this mode, the power to this block is still on but no bus clock is provided; hence, the logic is not functional.
All the configuration registers will keep their state.