110 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Timer, Counter, and PWM
16.3.2 Capture Mode
In the capture mode, the counter value can be captured at any time either through a firmware write to command register
(TCPWM_CMD) or a capture trigger input. This mode is used for period and pulse width measurement.
16.3.2.1 Block Diagram
Figure 16-6. Capture Mode Block Diagram
16.3.2.2 How it Works
The counter can be set to count in up, down, and up/down counting modes by configuring the UP_DOWN_MODE[17:16] bit-
field of the counter control register (TCPWM_CNT_CTRL).
Operation in capture mode occurs as follows:
■ During a capture event, generated either by hardware or software, the current count register value is copied to the capture
register (TCPWM_CNT_CC) and the capture register value is copied to the buffer capture register
(TCPWM_CNT_CC_BUFF).
■ A pulse on the CC output signal is generated when the counter value is copied to the capture register. This condition can
also be used to generate an interrupt request.
Figure 16-7 illustrates the capture behavior in the up counting mode.
Figure 16-7. Timing Diagram of Counter in Capture Mode, Up Counting Mode
PERIOD
COUNTER
CAPTURE
CAPTURE BUFFER
==
Reload
Start
Stop
Count
UN
OV
CC
TC
counter_clock
Capture
Period
Counter
OV
UN
TC
Capture, up counting mode
capture
capture buffer
CC
counter_clock
0xFFFF
Capture trigger
0x0002
0x0002
0xFFFE
0xFFFE
0x0003
0xFFFE
0xFFFF
0x0002
0x0003
0x0000
0x0001
0xFFFE
0xFFFF
0x0002
0x0003
0x0001
0x0002
0x0001
0xFFFF
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