Cypress PSoC 4000 Series - Capsense Clock Generator; Sigma Delta Converter

PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 131
CapSense
Figure 17-7. Sinking Current From AMUXBUS A
Figure 17-8. Voltage Across Sensor Capacitance
Equation 23-4 gives the value of average current taken from
AMUXBUS A.
Equation 17-3
The sigma delta converter scans one sensor at a time.
AMUXBUS A is used to select one of the GPIO cells and
connects it to the input of the sigma delta converter, as
Figure 17-3 shows. The AMUXBUS A and the GPIO cell
switches (see SW
3
in Figure 17-4) form this analog multi-
plexer. AMUXBUS A can connect to 16 PSoC 4 pins that
support CSD. See the device datasheet to know the CSD
capable pins.
See the I/O System chapter on page 45 to know how to con-
figure a GPIO cell for sensing, shielding, and connecting
C
MOD
.
17.4.2 CapSense Clock Generator
This block, together with the peripheral clock from the sys-
tem resources, generates the switching clock F
SW
and the
modulation clock F
MOD
, as Figure 17-3 shows. For details,
see the Clocking System chapter on page 55.
The switching clock is required for the GPIO cell switched
capacitance circuits. The sigma delta converter uses the
modulation clock for timing.
Two peripheral clocks CSDCLK0 and CSDCLK1 from the
system resources can be used to generate the required fre-
quencies. See the Clocking System chapter on page 55 for
details. CSDCLK0 generates modulation clock and
CSDCLK1 generates switching clock.
However, the final switching clock frequency depends on the
CapSense clock generator. It has the following output
options:
■ Direct: Uses the output of programmable clock dividers
directly. To select this option, set the BYPASS_SEL bit in
the CSD_CONFIG register ‘1’.
■ Divide by 2. Divides the clocks by two. To select this
option, clear the PRS_SELECT and BYPASS_SEL bits
in the CSD_CONFIG register.
■ Pseudo random sequence (PRS): Reduces the EMI in
the CapSense system by spreading the switching fre-
quency over a broader range. To select this option, set
the PRS_SELECT bit and clear the BYPASS_SEL bit in
the CSD_CONFIG register. You can select between 8-
and 12- bit pseudo random sequence using the
PRS_12_8 bit in the same register. Set this bit to select a
12- bit sequence; clear it for 8- bit PRS.
If PRS is selected, the maximum switching frequency is
Equation 17-4
Where F
in
is the frequency output of the CSDCLK1. The
minimum frequency is:
Equation 17-5
Where PRS length is either 12 or 8 bits. The average
switching frequency is:
Equation 17-6
The PRS_CLEAR bit in CSD_CONFIG can be used to clear
the PRS; when set, this bit forces the pseudo-random gen-
erator to its initial state.
17.4.3 Sigma Delta Converter
The sigma delta converter converts the input current to a
corresponding digital count. It consists of a comparator, a
voltage reference V
REF
, a counter, and two current sourcing/
C
S
R
S
AMUXBUS A
SW
1
SW
3
AMUXBUS A
I
SW
I
SW
I
SW
V
t
V
REF
(1.2 V)
0
T
SW
= 1/F
SW
SW
1
Open
SW
3
Closed
SW
1
Closed
SW
3
Open
I
S
C
S
F
SW
V
REF
=
F
SW maximum
F
in
2
-------=
F
SW minimum
F
in
PRS length-1
--------------------------------=
F
SW average
F
in
4
-------=