Cypress PSoC 4000 Series - Section B: CPU System

PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 23
Section B: CPU System
This section encompasses the following chapters:
■ Cortex-M0 CPU chapter on page 25
■ Interrupts chapter on page 31
Top Level Architecture
CPU System Block Diagram
SWD/TC
Cortex-M0
16 MHz (14 DMIPS)
NVIC, IRQMX
System Interconnect (Single Layer AHB)