Cypress PSoC 4000 Series - Digital Output Driver

48 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
I/O System
These buffer modes are selected by the PORT_VTRIP_SEL
bit (GPIO_PRTx_PC[24]) of the Port Configuration register.
The threshold values for each mode can be obtained from
the device datasheet. The output of the input buffer is con-
nected to the HSIOM for routing to the selected peripherals.
Writing to the HSIOM port select register
(HSIOM_PORT_SELx) selects the peripheral. The digital
input peripherals in the HSIOM, shown in Figure 7-2, are pin
dependent. See the device datasheet to know the functions
available for each pin.
7.3.2 Digital Output Driver
Pins are driven by the digital output driver. It consists of cir-
cuitry to implement different drive modes and slew rate con-
trol for the digital output signals. The peripheral connects to
the digital output driver through the HSIOM; a particular
peripheral is selected by writing to the HSIOM port select
register (HSIOM_PORT_SELx).
PSoC 4000 has a dedicated I/O supply voltage pin VDDIO in
the 16-QFN package; in the remaining devices, I/Os are
driven with the VDD supply. Each GPIO pin has ESD diodes
to clamp the pin voltage to the I/O supply source. Ensure
that the voltage at the pin does not exceed the I/O supply
voltage V
DDIO
/V
DD
and drop below V
SS
. For the absolute
maximum and minimum GPIO voltage, see the device data-
sheet. The digital output driver can be enabled and disabled
using the DSI signal from the peripheral or data register
(GPIO_PRTx_DR) associated with the output pin. See 7.4
High-Speed I/O Matrix to know about the peripheral source
selection for the data and to enable or disable control source
selection.
7.3.2.1 Drive Modes
Each I/O is individually configurable into one of eight drive
modes using the Port Configuration register,
GPIO_PRTx_PC. Table 7-2 lists the drive modes. Figure 7-2
is a simplified output driver diagram that shows the pin view
based on each of the eight drive modes.
Table 7-1. Input Buffer Modes
PORT_VTRIP_SEL Input Buffer Mode
0b CMOS
1b LVTTL
Table 7-2. Drive Mode Settings
GPIO_PRTx_PC ('x' denotes port number and 'y' denotes pin number)
Bits Drive Mode Value Data = 1 Data = 0
3y+2: 3y
SEL'y’ Selects Drive Mode for Pin 'y' (0
 y  7)
High-Impedance Analog 0 High Z High Z
High-impedance Digital 1 High Z High Z
Resistive Pull Up 2 Weak 1 Strong 0
Resistive Pull Down 3 Strong 1 Weak 0
Open Drain, Drives Low 4 High Z Strong 0
Open Drain, Drives High 5 Strong 1 High Z
Strong Drive 6 Strong 1 Strong 0
Resistive Pull Up and Down 7 Weak 1 Weak 0