PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 35
Interrupts
5.4.6 SysTick Exception
CM0 CPU in PSoC 4 supports a system timer, referred to as
SysTick, as part of its internal architecture. SysTick provides
a simple, 24-bit decrementing counter for various timekeep-
ing purposes such as an RTOS tick timer, high-speed alarm
timer, or simple counter. The SysTick timer can be config-
ured to generate an interrupt when its count value reaches
zero, which is referred to as SysTick exception. The excep-
tion is enabled by setting the TICKINT bit in the SysTick
Control and Status Register (CM0_SYST_CSR). The priority
of a SysTick exception can be configured to a value
between 0 and 3 by writing to the two bit fields
PRI_15[31:30] of the System Handler Priority Register 3
(SHPR3). The SysTick exception can always be generated
in software at any instant by writing a one to the PENDST-
SETb bit in the Interrupt Control State Register, CM0_ICSR.
Similarly, the pending state of the SysTick exception can be
cleared by writing a one to the PENDSTCLR bit in the Inter-
rupt Control State Register, CM0_ICSR.
5.5 Interrupt Sources
PSoC 4 supports nine interrupts (IRQ0 to IRQ8 or exception
numbers 16 – 24) from peripherals. The source of each
interrupt is listed in Table 5-3. PSoC 4 provides flexible
sourcing options for each of the nine interrupt lines. The
interrupts include standard interrupts from the on-chip
peripherals such as TCPWM serial communication block,
CSD block, and interrupts from ports. The interrupt gener-
ated is usually the logical OR of the different peripheral
states. The peripheral status register should be read in the
ISR to detect which condition generated the interrupt. These
interrupts are usually level interrupts, which require that the
peripheral status register be read in the ISR to clear the
interrupt. If the status register is not read in the ISR, the
interrupt will remain asserted and the ISR will be executed
continuously.
See the I/O System chapter on page 53 for details on GPIO
interrupts.
5.6 Exception Priority
Exception priority is useful for exception arbitration when
there are multiple exceptions that need to be serviced by the
CPU. PSoC 4 provides flexibility in choosing priority values
for different exceptions. All exceptions other than Reset,
NMI, and HardFault can be assigned a configurable priority
level. The Reset, NMI, and HardFault exceptions have a
fixed priority of –3, –2, and –1 respectively. In PSoC 4, lower
priority numbers represent higher priorities. This means that
the Reset, NMI, and HardFault exceptions have the highest
priorities. The other exceptions can be assigned a configu-
rable priority level between 0 and 3.
PSoC 4 supports nested exceptions in which a higher prior-
ity exception can obstruct (interrupt) the currently active
exception handler. This pre-emption does not happen if the
incoming exception priority is the same as active exception.
The CPU resumes execution of the lower priority exception
handler after servicing the higher priority exception. The
CM0 CPU in PSoC 4 allows nesting of up to four exceptions.
When the CPU receives two or more exceptions requests of
the same priority, the lowest exception number is serviced
first.
The registers to configure the priority of exception numbers
1 to 15 are explained in “Exception Sources” on page 33.
The priority of the nine interrupts (IRQ0 to IRQ8) can be
configured by writing to the Interrupt Priority registers
(CM0_IPR). This is a group of four 32-bit registers with each
register storing the priority values of four interrupts, as given
in Table 5-3. The other bit fields in the register are not used.
Table 5-2. List of PSoC 4 Interrupt Sources
Interrupt
Cortex-M0
Exception No.
Interrupt Source
NMI (see “Exception Sources” on
page 33)
2–
IRQ0 16 GPIO Interrupt - Port 0
IRQ1 17 GPIO Interrupt - Port 1
IRQ2 18 GPIO Interrupt - Port 2
IRQ3 19 GPIO Interrupt - Port 3
IRQ4 20 WDT (Watchdog timer) or Temp
IRQ5 21 SCB (Serial Communication Block)
IRQ6 22 SPC (System Performance Controller)
IRQ7 23 CSD (CapSense block counter overflow interrupt)
IRQ8 24 TCPWM0 (Timer/Counter/PWM 0)
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