Cypress PSoC 4000 Series - Stack Usage for Exceptions; Interrupts and Low-Power Modes

PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 37
Interrupts
Table 5-6 shows the register access properties for these two
registers. Note that writing zero to these registers has no
effect.
Setting the pending bit when the same bit is already set
results in only one execution of the ISR. The pending bit can
be updated regardless of whether the corresponding
interrupt is enabled. If the interrupt is not enabled, the
interrupt line will not move to the pending state until it is
enabled by writing to the CM0_ISER register.
Note that the CM0_ISPR and CM0_ICPR registers are used
only for the nine peripheral interrupts (exception numbers
16–47). These registers cannot be used for pending the
exception numbers 1 to 11. These 15 exceptions have their
own support for pending, as explained in “Exception
Sources” on page 33.
5.9 Stack Usage for Exceptions
When the CPU executes the main code (in thread mode)
and an exception request occurs, the CPU stores the state
of its general-purpose registers in the stack. It then starts
executing the corresponding exception handler (in handler
mode). The CPU pushes the contents of the eight 32-bit
internal registers into the stack. These registers are the
Program and Status Register (PSR), ReturnAddress, Link
Register (LR or R14), R12, R3, R2, R1, and R0. Cortex-M0
has two stack pointers - MSP and PSP. Only one of the
stack pointers can be active at a time. When in thread mode,
the Active Stack Pointer bit in the Control register is used to
define the current active stack pointer. When in handler
mode, the MSP is always used as the stack pointer. The
stack pointer in Cortex-M0 always grows downwards and
points to the address that has the last pushed data.
When the CPU is in thread mode and an exception request
comes, the CPU uses the stack pointer defined in the
control register to store the general-purpose register
contents. After the stack push operations, the CPU enters
handler mode to execute the exception handler. When
another higher priority exception occurs while executing the
current exception, the MSP is used for stack push/pop
operations, because the CPU is already in handler mode.
See the Cortex-M0 CPU chapter on page 35 for details.
The Cortex-M0 uses two techniques, tail chaining and late
arrival, to reduce latency in servicing exceptions. These
techniques are not visible to the external user and are part
of the internal processor architecture. For information on tail
chaining and late arrival mechanism, visit the ARM
Infocenter.
5.10 Interrupts and Low-Power
Modes
PSoC 4 allows device wakeup from low-power modes when
certain peripheral interrupt requests are generated. The
Wakeup Interrupt Controller (WIC) block generates a
wakeup signal that causes the device to enter Active mode
when one or more wakeup sources generate an interrupt
signal. After entering Active mode, the ISR of the peripheral
interrupt is executed.
The Wait For Interrupt (WFI) instruction, executed by the
CM0 CPU, triggers the transition into Sleep and Deep-Sleep
modes. The sequence of entering the different low-power
modes is detailed in the Power Modes chapter on page 75.
Chip low-power modes have two categories of fixed-function
interrupt sources:
■ Fixed-function interrupt sources that are available only in
the Active and Deep-Sleep modes (watchdog timer
interrupt, I2C interrupts, and GPIO interrupts)
■ Fixed-function interrupt sources that are available only in
the Active mode (all other fixed-function interrupts)
Table 5-6. Interrupt Set Pending/Clear Pending Registers
Register Operation
Bit
Value
Comment
Interrupt Set-
Pending Register
(CM0_ISPR)
Write
1
To put an interrupt to
pending state
0 No effect
Read
1 Interrupt is pending
0 Interrupt is not pending
Interrupt Clear-
Pending Register
(CM0_ICPR)
Write
1
To clear a pending
interrupt
0 No effect
Read
1 Interrupt is pending
0 Interrupt is not pending