148 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Nonvolatile Memory Programming
19.3 System Call Implementation
A system call consists of the following items:
■ Opcode: A unique 8-bit opcode
■ Parameters: Two 8-bit parameters are mandatory for all
system calls. These parameters are referred to as key1
and key2, and are defined as follows:
key1 = 0xB6
key2 = 0xD3 + Opcode
The two keys are passed to ensure that the user system
call is not initiated by mistake. If the key1 and key2
parameters are not correct, the SROM does not execute
the function, and returns an error code. Apart from these
two parameters, additional parameters may be required
depending on the specific function being called.
■ Return Values: Some system calls also return a value on
completion of their execution, such as the silicon ID or a
checksum.
■ Completion Status: Each system call returns a 32-bit sta-
tus that the CPU or DAP can read to verify success or
determine the reason for failure.
19.4 Blocking and Non-Blocking
System Calls
System call functions can be categorized as blocking or
non-blocking based on the nature of their execution. Block-
ing system calls are those where the CPU cannot execute
any other task in parallel other than the execution of the sys-
tem call. When a blocking system call is called from a pro-
cess, the CPU jumps to the code corresponding in SROM.
When the execution is complete, the original thread execu-
tion resumes. Non-blocking system calls allow the CPU to
execute some other code in parallel and communicate the
completion of interim system call tasks to the CPU through
an interrupt.
Non-blocking system calls are only used when the CPU initi-
ates the system call. The DAP will only use system calls dur-
ing the programming mode and the CPU is halted during this
process.
The three non-blocking system calls are Non-Blocking Write
Row, Non-Blocking Program Row, and Resume Non-Block-
ing, respectively. All other system calls are blocking.
Because the CPU cannot execute code from flash while
doing an erase or program operation on the flash, the non-
blocking system calls can only be called from a code execut-
ing out of SRAM. If the non-blocking functions are called
from flash memory, the result is undefined and may return a
bus error and trigger a hard fault when the flash fetch opera-
tion is being done.
The System Performance Controller (SPC) is the block that
generates the properly sequenced high-voltage pulses
required for erase and program operations of the flash mem-
ory. When a non-blocking function is called from SRAM, the
SPC timer triggers its interrupt when each of the sub-opera-
tions in a write or program operation is complete. Call the
Resume Non-Blocking function from the SPC interrupt ser-
vice routine (ISR) to ensure that the subsequent steps in the
system call are completed. Because the CPU can execute
code only from the SRAM when a non-blocking write or pro-
gram operation is being done, the SPC ISR should also be
located in the SRAM. The SPC interrupt is triggered once in
the case of a non-blocking program function or thrice in a
non-blocking write operation. The Resume Non-Blocking
function call done in the SPC ISR is called once in a non-
blocking program operation and thrice in a non-blocking
write operation.
The pseudo code for using a non-blocking write system call
and executing user code out of SRAM is given later in this
chapter.
19.4.1 Performing a System Call
The steps to initiate a system call are as follows:
1. Set up the function parameters: The two possible meth-
ods for preparing the function parameters (key1, key2,
additional parameters) are:
a. Write the function parameters to the
CPUSS_SYSARG register: This method is used for
functions that retrieve their parameters from the
CPUSS_SYSARG register. The 32-bit
CPUSS_SYSARG register must be written with the
parameters in the sequence specified in the respec-
tive system call table.
b. Write the function parameters to SRAM: This method
is used for functions that retrieve their parameters
from SRAM. The parameters should first be written in
the specified sequence to consecutive SRAM loca-
tions. Then, the starting address of the SRAM, which
is the address of the first parameter, should be writ-
ten to the CPUSS_SYSARG register. This starting
address should always be a word-aligned (32-bit)
address. The system call uses this address to fetch
the parameters.
2. Specify the system call using its opcode and initiating the
system call: The 8-bit opcode should be written to the
SYSCALL_COMMAND bits ([15:0]) in the
CPUSS_SYSREQ register. The opcode is placed in the
lower eight bits [7:0] and 0x00 be written to the upper
eight bits [15:8]. To initiate the system call, set the
SYSCALL_REQ bit (31) in the CPUSS_SYSREG regis-
ter. Setting this bit triggers a non-maskable interrupt that
jumps the CPU to the SROM code referenced by the
opcode parameter.
3. Wait for the system call to finish executing: When the
system call begins execution, it sets the PRIVILEGED bit
in the CPUSS_SYSREQ register. This bit can be set
only by the system call, not by the CPU or DAP. The
DAP should poll the PRIVILEGED and SYSCALL_REQ
bits in the CPUSS_SYSREG register continuously to
check whether the system call is completed. Both these
bits are cleared on completion of the system call. The
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